1. Field of the Invention
The present invention relates to clocked circuits.
2. Description of the Related Art
Synchronous sequential circuits rely on their clock signals for reliable operations. Clocked sequential elements such as flip-flops or registers transfer input data to output data at the transition of the clock signal. For proper loading, the input data have to meet the set-up and hold time requirements. Since these critical timing parameters are determined with respect to the clock signal, any clock skew or delay may cause timing violations, resulting in erroneous data loading. Delay is an amount of time by which a signal is retarded from a first point to a second point. Skew is a measure of divergence of the delay of a signal into two circuits. Clock skew is typically due to two causes. The first is uncontrolled differences in material and topology of the clock net. The second is the amount of delay introduced by the circuitry that generates a derived clock from a parent clock. Ideal clock delay and ideal clock skew are zero, and non-zero delay and skew typically must be compensated for. Clock skews and delays may also limit the operating frequency range, leading to degraded performance.
There are several sources that may cause clock skew in sequential circuits. One of the major sources is the use of gating circuitry to selectively enable or disable the clock signal. A typical gating circuitry may involve several levels of gating circuits, often in the form of AND or OR gates. These gates may introduce undesirable delays and cause unpredictable timing problems.
Routing is one source of delay. The problem is even more pronounced when circuits are prototyped in programmable devices such as field programmable logic arrays (FPGAs). In these programmable logic devices, the gated clock signals are typically routed on the general routing network due to the limited number of available dedicated clock routing networks. The general routing network usually introduces significant and unequal delays in the distribution of clocking signals to various sequential elements, causing clock skews at the clock inputs of the sequential elements.
One technique to reduce clock skew is to use delay elements at various points in the clock signal paths to compensate for the unequal delays. This technique increases the amount of hardware and circuit complexity. In addition, the delay elements may have their own delay variations which may not compensate well. Finally, this technique is typically not applicable in FPGAs.